1. Technical Field
The present disclosure relates to a MOSFET layout and structure, more particularly to a MOSFET layout and structure with common source.
2. Description of Related Art
Following the miniaturization of the volume of electrical product, the request for metal oxide field effect transistor (MOSFET) is tended to be smaller scale, higher operating frequency and higher stability. In the MOSFET, the current densities and turn-on resistance may influence the operating frequency and stability of the MOSFET. Wherein, the current densities and the width of the gate are in direct proportion. The current densities and the length of the gate are in inverse proportion. A conventional method for raising the current densities is increasing the effective width of the gate. However, when the MOSFET applies to the power management circuit, it needs a capacity for the electrostatic discharge (ESD) and so the ESD protection circuit must have bigger drain and source to sustain the damage of the ESD current. But the foregoing method will also cause a question, for example, the bigger layout area and the lower integration of the MOSFET.
FIG. 1 is a schematic diagram of a conventional power MOSFET layout. Referring to FIG. 1, in a single MOSFET, a drain zone 10 is surrounded by a gate region 12. A source region 14 is distributed around the gate region 12. Beside from that, a body region 16 is distributed outside the source region 14. Such that the current densities are raised by increasing the effective width of the gate. As shown in FIG. 1, the body region 16 is located between two source regions 14 of two neighboring power MOSFET. Thus, the body region 16 is used in common by two neighboring power MOSFET.
However, the drain region 10 must sustain a high-voltage due to electrostatic discharge. The width of the drain region 10 is wider than the source region 14. So, the power MOSFET occupies bigger layout area, such that the integration of the MOSFET layout is still lower.
Therefore, it becomes important issue that how to hold the sustainable capacity for the electrostatic discharge (ESD) with smaller layout area to raise the integration of the MOSFET layout.